1. Field of the Invention
The present invention relates to an apparatus for testing a semiconductor device and, more particularly, to positioning of a packed semiconductor device in a test apparatus
2. Description of the Related Art
In a process for testing various electrical characteristics of a packed semiconductor device (to be referred to as an IC chip hereinafter), an IC chip as a target test object is inserted into a socket manufactured in correspondence with electrode terminals of the IC chip, thereby electrically connecting the IC chip to a tester. In recent years, however, even in the IC chip test process, demand has arisen for increasing the throughput. Therefore, a testing method is used, in which the IC chip is electrically connected to the tester through test terminals called probe pins.
As described above, in electrical connection of an IC chip through probe pins, in order to increase test precision, it is important to align the probe pins with electrode terminals of the IC chip with high precision. In addition, along with an increase in integration density of semiconductor devices, IC chips tend to have a large number of terminals and a small pitch between adjacent terminals. When such an IC chip is to be tested, highly precise positioning is required
As this highly precise positioning method, electrode terminals of an IC chip placed on a test table are graphically recognized using, e.g., a camera, and positioning is performed on the basis of this image information.
In the positioning method which employs the image recognition technique described above, however, the operation time including an image recognition time is prolonged. In addition, since image recognition must be performed for each of the IC chips, a long positioning time is required and test efficiency of IC chips is degraded, resulting in inconvenience. Although test efficiency of IC chips is intended to be improved using probe pins, a test efficiency improvement effect using the probe pins cannot be sufficiently enhanced. Further, when the positioning method using image recognition is applied, the apparatus itself becomes expensive, and degradation of versatility may be caused.
Under these circumstances, strong demand has arisen for developing a relatively inexpensive test apparatus for semiconductor devices, which is capable of performing high-precision, high-speed positioning in order to accurately test IC chips at high speed.